The present application claims benefit of the filing date of U.S. provisional application No. 60/322,255, filed on Sep. 13, 2001, the entire content of which is incorporated herein by reference.
The present invention relates to integrated circuits (IC) containing programmable logic, and more particularly to a programmable interconnect structure for use in such ICs.
Advances in semiconductor fabrication processes which have enabled an ever increasing number of transistors to be formed on an IC fabricated on a single semiconductor substrate, and have seen a parallel increase in the type and number of functions that such ICs may perform. One class of ICs, commonly referred to as programmable logic devices (PLD), enables its users to program the functions that the PLD is to perform. The various hardware blocks, commonly known as logic blocks, in a PLD are typically not electrically connected to one another when the PLD is first supplied by its manufacturer. The user must first program the PLD to carry out the functions specified by the user. Programming of a PLD is usually performed with the aid of software in which the interconnections between various logic blocks are first specified, either by means of a table or a list of Boolean functions. After being executed, the software causes the specified interconnections to occur, in other words, it programs the PLD to create the desired logic and interconnections. A PLD thus eliminates the need for design-intensive and time-consuming efforts required for custom-specific ICs
A PLD usually includes arrays of logic cells, known as logic blocks, that are programmable and are selectively connected to arrays of interconnect lines to attain both combinatorial as well as sequential logic functions. Programming of programmable logic blocks, as well as their connections to the selected lines (e.g., bus lines), is typically achieved by establishing the states of a multitude of programmable elements, such as memory cells or fuses, disposed in the PLD. The logic blocks disposed in a PLD often arc divided into arrays of AND and OR functions, adapted to perform the specified functions.
One type of PLD is programmable array logic (PAL). In a PAL, the AND arrays are programmable, while the OR arrays are fixed. Accordingly, in a PAL, the AND gates are programmed to provide the product term logic signals which are subsequently summed by the OR gates.
Another type of PLD is known as programmable logic array (PLA) in which both the AND and OR arrays are programmable. In a PLA, the product terms in the AND array may be shared by the OR array to provide the specified logic functions. Both PALs and PLAs often include flip-flops, in addition to the AND and OR arrays, to provide sequential logic operations.
A disadvantage of both PALs and PLAs is their logic utilization. In other words, after being configured, some of the logic blocks disposed within a PLD may remain unutilized. To increase their utilization, PLDs have been adapted to include one or more macro cells. A macro cell is a logic block or a group of logic blocks that may be configured to perform many different and relatively more complex logic functions. A macro cell may be selectively interconnected to other macro cells or logic blocks. Macro cells enable attainment of a more granular structure and, therefore, increase the utilization of the semiconductor surface area in which the PLD is formed and, therefore, reduce cost.
Another type of IC which integrates a number of macro cells, analog and/or memory blocks on the same silicon substrate is commonly referred to as system-on-chip (SoC). An SoC may be configured to perform functions that would otherwise require several different ICs to perform.
The macro cells disposed in a conventional SoC are typically either hard wired during the fabrication process or are later programmed (i.e., configured) following the fabrication process. If hardwired during the fabrication process, an SoC may not be reconfigured following the completion of the fabrication process. If not configured during the fabrication process, an SoC is often configured with the aid of software. Such configuration software may be subsequently used to reconfigure the SoC to enable it to perform functions that are different from those for which the SoC was configured before. A reconfigurable SoC often employs arrays of interconnects which are selectively coupled to one another to provide the specified logic functions.
FIG. 2 of U.S. Pat. No. 5,504,440, issued to Sasaki, illustrates an interconnection between a logic cell 20 and input and output buses 23 and 17. Each line of bus 12 is shown as being coupled to an input terminal of logic cell 20 via xe2x80x9ca programmable three state buffer operating under control of an input signal supplied to it on line 54. Line 54 is coupled to a register or other means within which the program for controlling the overall programmable logic device is stored.xe2x80x9d
As disclosed in Sasaki, xe2x80x9cA separate bit in this register, memory, a fuse or other means, is used to control a corresponding one of the programmable connections in the drawing in FIG. 2. Other bits are used to control other programmable connections elsewhere in the programmable logic device. Thus the control memory typically will have as many bits stored therein as there are programmable connections to be controlled. Of course, where two configurations are mutually exclusive and one, and only one, is always provided, the complementary state of a single bit can control two configurations. Under control of the memory bit, circuit 52a is either active or in a high impedance state. When the input 54a is enabled, circuit 52a repeats the signal coupled to its input node 57a. In other words, if a logical 1 is present on conductor 12a of bus 12, then input node 57a of driver 52a will be a logical 1. Assuming that control line 54a is enabled, then the output from driver 52a will also be a logical 1. Of course, the same conditions apply if a logical 0 is present on conductor 12a. Each of the drivers 52 functions in the same manner. On the other hand, if control line 54 is not enabled, then the driver circuits present a high impedance state and functionally behave as an open circuit. In other words, node 55 is completely disconnected from bus 12. This allows an input node 41 to be disconnected from the bus 12 when that input node is not to receive signals from bus 12.xe2x80x9d
FIG. 9A of U.S. Pat. No. 4,870,302, issued to Freeman, is the schematic of a circuit for making a number of different interconnections. xe2x80x9cThus, in FIG. 9A, pass transistor 2, when activated into the conducting state, connects lead 90-3 to lead 90-1. Pass transistor 1, when conducting, connects lead 90-3 to lead 90-4. Pass transistor 4, when conducting, connects lead 90-4 to lead 90-2 and pass transistor 3, when conducting, connects lead 90-1 to lead 90-2. Pass transistors 6 and 5, when off, separate lead 90-2 from lead 90-3 and separate lead 90-1 from lead 90-4 respectively. Thus, should it be desired to connect vertical lead 90-2 to vertical lead 90-3, pass transistor 6 is activated. Likewise, should it be desired to connect horizontal lead 90-1 to horizontal lead 90-4, pass transistor 5 is activated.xe2x80x9d
Conventional interconnect structures of the types that are deployed in known PLDs or SoCs may limit the reconfigurability of the macro cells disposed therein and may also limit the speed of operation. Such problems are further compounded as the supply voltages continue to scale down.
A programmable interconnect structure (hereinafter referred to as connector), in accordance with the present invention, includes two separate paths. Disposed within the first path are first and second CMOS transmission gates (hereinafter referred to as transmission gates) and a first buffer. Disposed within the second path are third and fourth transmission gates and a second buffer. A first terminal of the first transmission gate is coupled to a first terminal of the connector. A second terminal of the first transmission gate is coupled to an input terminal of the first buffer. An output terminal of the first buffer is coupled to an input terminal of the second transmission gate whose second terminal is coupled to the second terminal of the connector. Similarly, a first terminal of the third transmission gate is coupled to the second terminal of the connector. A second terminal of the third transmission gate is coupled to an input terminal of the second buffer. An output terminal of the second buffer is coupled to an input terminal of the fourth transmission gate whose second terminal is coupled to the first terminal of the connector. The gate terminals of the NMOS transistors of both the first and second transmission gates receive a first voltage supplied by a first programmable memory element. The gate terminals of the PMOS transistors of both the first and second transmission gates receive a second voltage supplied by the first programmable memory element. The first and second voltages supplied by the first programmable memory elements are complements of one another. The gate terminals of the NMOS transistors of both the third and fourth transmission gates receive a third voltage supplied by a second programmable memory element. The gate terminals of the PMOS transistors of both the third and fourth transmission gates receive a fourth voltage supplied by the second programmable memory element. The third and fourth voltages supplied by the second programmable memory elements are complements of one another.
If the first and third voltages supplied by the first and second programmable memory elements are respectively at high and low levels, the first and second transmission gates are closed while the third and fourth transmission gates are open. Consequently, the first path is in a conducting state and the second path is in a non-conducting state, therefore, current may flow only from the first terminal to the second terminal of the connector.
If the first and third voltages supplied by the first and second programmable memory elements are respectively at low and high levels, the first and second transmission gates are open while the third and fourth transmission gates are closed. Consequently, the first path is in a conducting state and the second path is in a non-conducting state, therefore, current may flow only from the second terminal to the first terminal of the connector.
If the first and third voltages supplied respectively by the first and second programmable memory elements both are at low levels, all four transmission gates are open. Consequently, both the first and second paths are in non-conducting states and, therefore, current flow between the first and second terminals of the connector is inhibited.
The third transmission gate isolates the output terminal of the first buffer from the input terminal of the second bufferxe2x80x94when the connector is configured to transfer signal from its first terminal to its second terminal. Since, the first buffer is not loaded with the input capacitance of the second buffer, power consumption is reduced. Similarly, the first transmission gate isolates the output terminal of the second buffer from the input terminal of the first bufferxe2x80x94when the connector is configured to transfer signal from its second terminal to its first terminal. Since, the second buffer is not loaded with the input capacitance of the first buffer, power consumption is reduced.
The connector further includes a first NMOS transistor associated with the first path and a second NMOS transistor associated with the second path. The drain terminal of the first NMOS transistor is coupled to the input terminal of the first buffer. The source terminal of the first NMOS transistor is coupled to the ground. The gate terminal of the first NMOS transistor is coupled to the second voltage supplied by the first programmable memory element. The drain terminal of the second NMOS transistor is coupled to the input terminal of the second buffer. The source terminal of the second NMOS transistor is coupled to the ground. The gate terminal of the second NMOS transistor is coupled to the fourth voltage supplied by the second programmable memory element. If the first path is open, the first NMOS transistor is on, thereby coupling the input terminal of the first buffer to the ground. Similarly, if the second path is open, the second NMOS transistor is on, thereby coupling the input terminal of the second buffer to the ground.
The buffer in each of the first and second paths reduces the rise and fall times of the signal applied thereto, thereby restoring the signal""s shape. The programmable memory elements are programmed during the programming phase, and depending oil the values stored therein, either open or close the transmission gates that they are coupled to.
In accordance with some embodiments of the present invention, each buffer may include one or more CMOS inverters. Each programmable memory element may be a fuse, a non-volatile memory, such as an Electrically Erasable Programmable Read Only Memory (EEPROM), or a volatile memory, such a Static Random Access Memory (SRAM), or a register.